Trends in Submicrometer InP-Based HBT Architecture Targeting Thermal Management
Identifieur interne : 002207 ( Main/Repository ); précédent : 002206; suivant : 002208Trends in Submicrometer InP-Based HBT Architecture Targeting Thermal Management
Auteurs : RBID : Pascal:11-0367453Descripteurs français
- Pascal (Inist)
- Transistor bipolaire hétérojonction, Comportement thermique, Gestion température packaging électronique, Haute température, Propriété transport, Fiabilité, Résistance thermique, Passivation, Collecteur, Extensibilité, Conception assistée, Prospective, Etalonnage, Pastille électronique, Fixation pastille, Phosphure d'indium, Composé binaire, Nitrure de silicium, Conception circuit, Fabrication microélectronique, InP.
- Wicri :
- concept : Prospective.
English descriptors
- KwdEn :
- Binary compound, Calibration, Circuit design, Collector, Computer aided design, Heterojunction bipolar transistors, High temperature, Indium phosphide, Microelectronic fabrication, Passivation, Prospective, Reliability, Scalability, Silicon nitride, Thermal behavior, Thermal management (packaging), Thermal resistance, Transport properties, Wafer, Wafer bonding.
Abstract
More than ever, thermal management in InP-based heterojunction bipolar transistors (HBTs) is a critical issue since high junction temperature degrades transport properties and device reliability. This paper presents investigation results on the impact of device architecture enhancements aimed at reducing thermal resistance using alternative substrates or passivation materials or metallic collectors or all of them. Using 3-D scalable technology computer-aided design electrothermal simulations, the impact of these features is quantified. This prospective work is based on calibration measurements performed on InP bulk HBTs with various InGaAs subcollector thickness values. A wafer-bonded Si-substrate, a 25-nm-thin InGaAs subcollector, and SiN passivation are the key technological features that reduce the thermal resistance by 70%. An even more aggressive thermal management architecture using metallic collectors reduces the thermal resistance up to 80%.
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Pascal:11-0367453Le document en format XML
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Kone</name><affiliation wicri:level="4"><inist:fA14 i1="01"><s1>Université de Bordeaux, Integration du Matériau au Système, Centre National de la Recherche Scientifique, Unités Mixtes de Recherche 5218</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>8 aut.</sZ><sZ>9 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Aquitaine</region><settlement type="city">Talence</settlement></placeName><orgName type="university">Université de Bordeaux</orgName></affiliation></author><author><name sortKey="Hainaut, Cyril" uniqKey="Hainaut C">Cyril Hainaut</name><affiliation wicri:level="4"><inist:fA14 i1="01"><s1>Université de Bordeaux, Integration du Matériau au Système, Centre National de la Recherche Scientifique, Unités Mixtes de Recherche 5218</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>8 aut.</sZ><sZ>9 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Aquitaine</region><settlement type="city">Talence</settlement></placeName><orgName type="university">Université de Bordeaux</orgName></affiliation></author><author><name sortKey="Godin, Jean" uniqKey="Godin J">Jean Godin</name><affiliation wicri:level="3"><inist:fA14 i1="02"><s1>Alcatel-Thales III-V Lab, Route de Nozay</s1><s2>91461 Marcoussis</s2><s3>FRA</s3><sZ>2 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Île-de-France</region><settlement type="city">Marcoussis</settlement></placeName></affiliation></author><author><name sortKey="Riet, Muriel" uniqKey="Riet M">Muriel Riet</name><affiliation wicri:level="3"><inist:fA14 i1="02"><s1>Alcatel-Thales III-V Lab, Route de Nozay</s1><s2>91461 Marcoussis</s2><s3>FRA</s3><sZ>2 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Île-de-France</region><settlement type="city">Marcoussis</settlement></placeName></affiliation></author><author><name sortKey="Zimmer, Thomas" uniqKey="Zimmer T">Thomas Zimmer</name><affiliation wicri:level="4"><inist:fA14 i1="01"><s1>Université de Bordeaux, Integration du Matériau au Système, Centre National de la Recherche Scientifique, Unités Mixtes de Recherche 5218</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>8 aut.</sZ><sZ>9 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Aquitaine</region><settlement type="city">Talence</settlement></placeName><orgName type="university">Université de Bordeaux</orgName></affiliation></author><author><name sortKey="Maneux, Cristell" uniqKey="Maneux C">Cristell Maneux</name><affiliation wicri:level="4"><inist:fA14 i1="01"><s1>Université de Bordeaux, Integration du Matériau au Système, Centre National de la Recherche Scientifique, Unités Mixtes de Recherche 5218</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>8 aut.</sZ><sZ>9 aut.</sZ></inist:fA14><country>France</country><placeName><region type="region" nuts="2">Aquitaine</region><settlement type="city">Talence</settlement></placeName><orgName type="university">Université de Bordeaux</orgName></affiliation></author></titleStmt><publicationStmt><idno type="inist">11-0367453</idno><date when="2011">2011</date><idno type="stanalyst">PASCAL 11-0367453 INIST</idno><idno type="RBID">Pascal:11-0367453</idno><idno type="wicri:Area/Main/Corpus">002B77</idno><idno type="wicri:Area/Main/Repository">002207</idno></publicationStmt><seriesStmt><idno type="ISSN">0018-9383</idno><title level="j" type="abbreviated">IEEE trans. electron devices</title><title level="j" type="main">I.E.E.E. transactions on electron devices</title></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Binary compound</term><term>Calibration</term><term>Circuit design</term><term>Collector</term><term>Computer aided design</term><term>Heterojunction bipolar transistors</term><term>High temperature</term><term>Indium phosphide</term><term>Microelectronic fabrication</term><term>Passivation</term><term>Prospective</term><term>Reliability</term><term>Scalability</term><term>Silicon nitride</term><term>Thermal behavior</term><term>Thermal management (packaging)</term><term>Thermal resistance</term><term>Transport properties</term><term>Wafer</term><term>Wafer bonding</term></keywords><keywords scheme="Pascal" xml:lang="fr"><term>Transistor bipolaire hétérojonction</term><term>Comportement thermique</term><term>Gestion température packaging électronique</term><term>Haute température</term><term>Propriété transport</term><term>Fiabilité</term><term>Résistance thermique</term><term>Passivation</term><term>Collecteur</term><term>Extensibilité</term><term>Conception assistée</term><term>Prospective</term><term>Etalonnage</term><term>Pastille électronique</term><term>Fixation pastille</term><term>Phosphure d'indium</term><term>Composé binaire</term><term>Nitrure de silicium</term><term>Conception circuit</term><term>Fabrication microélectronique</term><term>InP</term></keywords><keywords scheme="Wicri" type="concept" xml:lang="fr"><term>Prospective</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">More than ever, thermal management in InP-based heterojunction bipolar transistors (HBTs) is a critical issue since high junction temperature degrades transport properties and device reliability. This paper presents investigation results on the impact of device architecture enhancements aimed at reducing thermal resistance using alternative substrates or passivation materials or metallic collectors or all of them. Using 3-D scalable technology computer-aided design electrothermal simulations, the impact of these features is quantified. This prospective work is based on calibration measurements performed on InP bulk HBTs with various InGaAs subcollector thickness values. A wafer-bonded Si-substrate, a 25-nm-thin InGaAs subcollector, and SiN passivation are the key technological features that reduce the thermal resistance by 70%. An even more aggressive thermal management architecture using metallic collectors reduces the thermal resistance up to 80%.</div></front></TEI><inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>0018-9383</s0></fA01><fA02 i1="01"><s0>IETDAI</s0></fA02><fA03 i2="1"><s0>IEEE trans. electron devices</s0></fA03><fA05><s2>58</s2></fA05><fA06><s2>8</s2></fA06><fA08 i1="01" i2="1" l="ENG"><s1>Trends in Submicrometer InP-Based HBT Architecture Targeting Thermal Management</s1></fA08><fA11 i1="01" i2="1"><s1>GRANDCHAMP (Brice)</s1></fA11><fA11 i1="02" i2="1"><s1>NODJIADJIM (Virginie)</s1></fA11><fA11 i1="03" i2="1"><s1>ZAKNOUNE (Mohammed)</s1></fA11><fA11 i1="04" i2="1"><s1>KONE (Gilles A.)</s1></fA11><fA11 i1="05" i2="1"><s1>HAINAUT (Cyril)</s1></fA11><fA11 i1="06" i2="1"><s1>GODIN (Jean)</s1></fA11><fA11 i1="07" i2="1"><s1>RIET (Muriel)</s1></fA11><fA11 i1="08" i2="1"><s1>ZIMMER (Thomas)</s1></fA11><fA11 i1="09" i2="1"><s1>MANEUX (Cristell)</s1></fA11><fA14 i1="01"><s1>Université de Bordeaux, Integration du Matériau au Système, Centre National de la Recherche Scientifique, Unités Mixtes de Recherche 5218</s1><s2>33405 Talence</s2><s3>FRA</s3><sZ>1 aut.</sZ><sZ>4 aut.</sZ><sZ>5 aut.</sZ><sZ>8 aut.</sZ><sZ>9 aut.</sZ></fA14><fA14 i1="02"><s1>Alcatel-Thales III-V Lab, Route de Nozay</s1><s2>91461 Marcoussis</s2><s3>FRA</s3><sZ>2 aut.</sZ><sZ>6 aut.</sZ><sZ>7 aut.</sZ></fA14><fA14 i1="03"><s1>Institute of Electronics, Microelectronics, and Nanotechnology, Centre National de la Recherche Scientifique, Unités Mixtes de Recherche 8520</s1><s2>59652 Villeneuve d'Ascq</s2><s3>FRA</s3><sZ>3 aut.</sZ></fA14><fA20><s1>2566-2572</s1></fA20><fA21><s1>2011</s1></fA21><fA23 i1="01"><s0>ENG</s0></fA23><fA43 i1="01"><s1>INIST</s1><s2>222F3</s2><s5>354000508589360450</s5></fA43><fA44><s0>0000</s0><s1>© 2011 INIST-CNRS. All rights reserved.</s1></fA44><fA45><s0>27 ref.</s0></fA45><fA47 i1="01" i2="1"><s0>11-0367453</s0></fA47><fA60><s1>P</s1></fA60><fA61><s0>A</s0></fA61><fA64 i1="01" i2="1"><s0>I.E.E.E. transactions on electron devices</s0></fA64><fA66 i1="01"><s0>USA</s0></fA66><fC01 i1="01" l="ENG"><s0>More than ever, thermal management in InP-based heterojunction bipolar transistors (HBTs) is a critical issue since high junction temperature degrades transport properties and device reliability. This paper presents investigation results on the impact of device architecture enhancements aimed at reducing thermal resistance using alternative substrates or passivation materials or metallic collectors or all of them. Using 3-D scalable technology computer-aided design electrothermal simulations, the impact of these features is quantified. This prospective work is based on calibration measurements performed on InP bulk HBTs with various InGaAs subcollector thickness values. A wafer-bonded Si-substrate, a 25-nm-thin InGaAs subcollector, and SiN passivation are the key technological features that reduce the thermal resistance by 70%. An even more aggressive thermal management architecture using metallic collectors reduces the thermal resistance up to 80%.</s0></fC01><fC02 i1="01" i2="X"><s0>001D03F04</s0></fC02><fC02 i1="02" i2="X"><s0>001D03F06A</s0></fC02><fC02 i1="03" i2="X"><s0>001D03F17</s0></fC02><fC03 i1="01" i2="3" l="FRE"><s0>Transistor bipolaire hétérojonction</s0><s5>01</s5></fC03><fC03 i1="01" i2="3" l="ENG"><s0>Heterojunction bipolar transistors</s0><s5>01</s5></fC03><fC03 i1="02" i2="X" l="FRE"><s0>Comportement thermique</s0><s5>02</s5></fC03><fC03 i1="02" i2="X" l="ENG"><s0>Thermal behavior</s0><s5>02</s5></fC03><fC03 i1="02" i2="X" l="SPA"><s0>Comportamiento térmico</s0><s5>02</s5></fC03><fC03 i1="03" i2="3" l="FRE"><s0>Gestion température packaging électronique</s0><s5>03</s5></fC03><fC03 i1="03" i2="3" l="ENG"><s0>Thermal management (packaging)</s0><s5>03</s5></fC03><fC03 i1="04" i2="X" l="FRE"><s0>Haute température</s0><s5>04</s5></fC03><fC03 i1="04" i2="X" l="ENG"><s0>High temperature</s0><s5>04</s5></fC03><fC03 i1="04" i2="X" l="SPA"><s0>Alta temperatura</s0><s5>04</s5></fC03><fC03 i1="05" i2="X" l="FRE"><s0>Propriété transport</s0><s5>05</s5></fC03><fC03 i1="05" i2="X" l="ENG"><s0>Transport properties</s0><s5>05</s5></fC03><fC03 i1="05" i2="X" l="SPA"><s0>Propiedad transporte</s0><s5>05</s5></fC03><fC03 i1="06" i2="X" l="FRE"><s0>Fiabilité</s0><s5>06</s5></fC03><fC03 i1="06" i2="X" l="ENG"><s0>Reliability</s0><s5>06</s5></fC03><fC03 i1="06" i2="X" l="SPA"><s0>Fiabilidad</s0><s5>06</s5></fC03><fC03 i1="07" i2="X" l="FRE"><s0>Résistance thermique</s0><s5>07</s5></fC03><fC03 i1="07" i2="X" l="ENG"><s0>Thermal resistance</s0><s5>07</s5></fC03><fC03 i1="07" i2="X" l="SPA"><s0>Resistencia térmica</s0><s5>07</s5></fC03><fC03 i1="08" i2="X" l="FRE"><s0>Passivation</s0><s5>08</s5></fC03><fC03 i1="08" i2="X" l="ENG"><s0>Passivation</s0><s5>08</s5></fC03><fC03 i1="08" i2="X" l="SPA"><s0>Pasivación</s0><s5>08</s5></fC03><fC03 i1="09" i2="X" l="FRE"><s0>Collecteur</s0><s5>09</s5></fC03><fC03 i1="09" i2="X" l="ENG"><s0>Collector</s0><s5>09</s5></fC03><fC03 i1="09" i2="X" l="SPA"><s0>Colector</s0><s5>09</s5></fC03><fC03 i1="10" i2="X" l="FRE"><s0>Extensibilité</s0><s5>10</s5></fC03><fC03 i1="10" i2="X" l="ENG"><s0>Scalability</s0><s5>10</s5></fC03><fC03 i1="10" i2="X" l="SPA"><s0>Estensibilidad</s0><s5>10</s5></fC03><fC03 i1="11" i2="X" l="FRE"><s0>Conception assistée</s0><s5>11</s5></fC03><fC03 i1="11" i2="X" l="ENG"><s0>Computer aided design</s0><s5>11</s5></fC03><fC03 i1="11" i2="X" l="SPA"><s0>Concepción asistida</s0><s5>11</s5></fC03><fC03 i1="12" i2="X" l="FRE"><s0>Prospective</s0><s5>12</s5></fC03><fC03 i1="12" i2="X" l="ENG"><s0>Prospective</s0><s5>12</s5></fC03><fC03 i1="12" i2="X" l="SPA"><s0>Prospectiva</s0><s5>12</s5></fC03><fC03 i1="13" i2="X" l="FRE"><s0>Etalonnage</s0><s5>13</s5></fC03><fC03 i1="13" i2="X" l="ENG"><s0>Calibration</s0><s5>13</s5></fC03><fC03 i1="13" i2="X" l="SPA"><s0>Contraste</s0><s5>13</s5></fC03><fC03 i1="14" i2="X" l="FRE"><s0>Pastille électronique</s0><s5>14</s5></fC03><fC03 i1="14" i2="X" l="ENG"><s0>Wafer</s0><s5>14</s5></fC03><fC03 i1="14" i2="X" l="SPA"><s0>Pastilla electrónica</s0><s5>14</s5></fC03><fC03 i1="15" i2="X" l="FRE"><s0>Fixation pastille</s0><s5>15</s5></fC03><fC03 i1="15" i2="X" l="ENG"><s0>Wafer bonding</s0><s5>15</s5></fC03><fC03 i1="15" i2="X" l="SPA"><s0>Fijación pastilla</s0><s5>15</s5></fC03><fC03 i1="16" i2="X" l="FRE"><s0>Phosphure d'indium</s0><s5>22</s5></fC03><fC03 i1="16" i2="X" l="ENG"><s0>Indium phosphide</s0><s5>22</s5></fC03><fC03 i1="16" i2="X" l="SPA"><s0>Indio fosfuro</s0><s5>22</s5></fC03><fC03 i1="17" i2="X" l="FRE"><s0>Composé binaire</s0><s5>23</s5></fC03><fC03 i1="17" i2="X" l="ENG"><s0>Binary compound</s0><s5>23</s5></fC03><fC03 i1="17" i2="X" l="SPA"><s0>Compuesto binario</s0><s5>23</s5></fC03><fC03 i1="18" i2="X" l="FRE"><s0>Nitrure de silicium</s0><s5>24</s5></fC03><fC03 i1="18" i2="X" l="ENG"><s0>Silicon nitride</s0><s5>24</s5></fC03><fC03 i1="18" i2="X" l="SPA"><s0>Silicio nitruro</s0><s5>24</s5></fC03><fC03 i1="19" i2="X" l="FRE"><s0>Conception circuit</s0><s5>46</s5></fC03><fC03 i1="19" i2="X" l="ENG"><s0>Circuit design</s0><s5>46</s5></fC03><fC03 i1="19" i2="X" l="SPA"><s0>Diseño circuito</s0><s5>46</s5></fC03><fC03 i1="20" i2="X" l="FRE"><s0>Fabrication microélectronique</s0><s5>47</s5></fC03><fC03 i1="20" i2="X" l="ENG"><s0>Microelectronic fabrication</s0><s5>47</s5></fC03><fC03 i1="20" i2="X" l="SPA"><s0>Fabricación microeléctrica</s0><s5>47</s5></fC03><fC03 i1="21" i2="X" l="FRE"><s0>InP</s0><s4>INC</s4><s5>82</s5></fC03><fC07 i1="01" i2="X" l="FRE"><s0>Composé III-V</s0><s5>16</s5></fC07><fC07 i1="01" i2="X" l="ENG"><s0>III-V compound</s0><s5>16</s5></fC07><fC07 i1="01" i2="X" l="SPA"><s0>Compuesto III-V</s0><s5>16</s5></fC07><fN21><s1>249</s1></fN21><fN44 i1="01"><s1>OTO</s1></fN44><fN82><s1>OTO</s1></fN82></pA></standard></inist></record>Pour manipuler ce document sous Unix (Dilib)
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